REDUCED INSTRUCTION SEC COMPUTERS (RISC)

KEY FEATURES OF RISC & CISC

THE NEED FOR CISC

CISC FAULTS

TO CONTRAS CISC & RISC

By  Ahmad Nafis Hisyam

Chapter_3_Instruction_Set_Architecture Part1 & 2

By     Hong Yen Hau

Chapter 6 Input / Output

}I/O system consists of I/O devices ,device controllers and driver software.

}I/O Module Function

  a) Control & Timing

  -To coordinate flow of traffic between external devices and internal   resources.

 b)Processor Communication

  -For decoding in I/O module ,data exchange through data bus , status   reporting about peripheral , and CPU assigning unique address for   each I/O module.

 c)Device Communication

    -Device Communication involves commands ,status information and data.

d)Data Buffering

   -The data are buffered in the I/O module and then sent to the peripheral device at its data rate.

e)Error Detection

   -For reporting errors to the processor.

I/O Module Diagram

I/O Mapping

}Memory mapped I/O

   -Device and memory share an address space.

   -I/O looks just like memory read/write

   -No special commands for I/O.

}Isolated I/O

   -Separate address spaces

   -Need I/O or memory select lines

   -Special commands for I/O

Input Output Techniques

}Programmed I/O

   -Data are exchanged between the processor and the I/O module.

   -CPU has direct control over I/O

   -sensing status

   -read/write commands

   -transferring data

      -waste CPU time

Programmed I/O-Detail

}CPU requests I/O operation

}I/O module performs operation

}I/O module sets status bits

}CPU checks status bits periodically (known as polling)

}I/O module does not inform CPU directly

}I/O module does not interrupt CPU

}CPU may wait or come back later

Programmed I/O

}Interrupt Driven I/O

    -Overcomes CPU waiting

    -No repeated CPU checking of Device

    -I/O module interrupts when ready.

Interrupt Driven I/O-Basic Operation

}CPU issues read command

}I/O module gets data from peripheral whilst CPU does other work

}I/O module interrupts CPU

}CPU requests data

}I/O module transfers data

Interrupt Driven I/O

Interrupt I/O

}Interrupt I/O is more efficient than programmed I/O because it eliminates needless waiting. 

}Interrupt I/O consumes a lot of processor time, because data transfer from memory to I/O module to memory must passed through the processor.

Drawbacks of Programmed and Interrupt Driven I/O

     nBoth forms of I/O suffer from two inherent drawbacks:

1)The I/O transfer rate is limited by the speed with which the processor can test and service a device

2)The processor is tied up in managing an I/O transfer; a number of instructions must be executed for each I/O transfer

}Direct Memory Access

 -Interrupt driven and programmed I/O require active    CPU intervention

 -DMA is the answer.

 -Advantage :Large amounts of data can be transferred     between memory and the peripheral W/O severely impacting CPU performance.

Direct Memory Access

DMA Function

}Additional Module (hardware) on bus

}DMA controller takes over from CPU for I/O

Direct Memory Access

DMA Transfer – Cycling Stealing

}In cycling-stealing ,DMA controller acquires the bus ,transfer a single byte or word for a cycle.

}Cycling-stealing is not an interruption because CPU dose not switch context.

}CPU suspend just before it accesses bus.

}This allow other devices , and in particular the CPU , to share the bus during DMA transfers.

}Slow down CPU.

DMA Configurations(1)

}Single Bus ,Detached DMA controller

}Each transfer uses bus twice

}CPU is suspended twice

DMA Configurations(2)

}Single Bus ,Integrated DMA controller

}DMA Controller may support>1 device

}Each transfer uses bus once

}CPU is suspended once

DMA Configuration(3)

}Separate I/O Bus

}Bus supports all DMA enable devices

}Each transfer uses bus once

}CPU is suspended once

By     Fam Jiang Yuan

Chapter 2 : Data Representation

           Data Types

• Represented in binary-coded form.
•  Only have 0 & 1 to represent everything.

The Decimal Number System

·         The Base 10 number system uses the digit: 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9.

                      

Example : The number 81 means eight tens plus one:

                                     81=(8*10) + 1

           The Binary Number System

•   A variable whose value may be either 0 or 1.
• Bits are organized into groups of 8 called bytes.
• Represented to the base 2

                   Example: 10₂ = ( 1 * 2¹ )  + ( 0 * 2⁰ ) = 2₁₀

             The Octal Number System

•  Base-8 number system
• Uses the digits 0, 1, 2, 3, 4, 5, 6, 7.

           The Hexadecimal Number System 

• The hexadecimal number system uses the following digits:

0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F

Number Conversion

 

Two’s complement benefit

•  One representation of zero
•  Arithmetic works easily
• Range for a word length of n bits :  -(2^n-1) à (2^n-1 – 1)

By     Kuan Wei Sern

Chapter 5: Bus System

A communication pathway connecting two or more devices.

Components of the system bus and attached devices.

•   Internal and External bus

Internal bus – a bus located strictly within a CPU chip for communication among the components in  a CPU chip.
External bus – outside a CPU chip for connecting the rest of the system components to the CPU.

• System bus consist of a common set of parallel wires : 

i) Address buses
ii) Data buses
iii) Control buses

• Bus hierarchy

i) the processor bus (system bus)

ii) the cache bus (backside bus)
iii) the memory bus
iv) the local I/O bus (high speed I/O bus)
v) the standard I/O bus

·         Characteristics of Bus

i) Data and address buses

ii) Bus width

iii) Bus speed

iv) Bus Bandwidth

* For very slow bus, bandwidth = ½ (bus width x bus speed)

·         Performance of a bus

i) Transfer time – amount of time it takes for data to be delivered in a single transaction.

ii) Bandwidth – units of bits per second (bps), measures the capacity of the bus.

• System Board

·         Bus standards

i) Industry Standard Architecture (ISA) Bus
  - the most common bus in the PC world
ii) Micro Channel Architecture (MCA) Bus
  - MCA also called the Micro Channel bus
iii) Extended Industry Standard Architecture (EISA) bus
  - EISA bus never became widely used and cannot be considered an industry standard.
iv) VESA Local Bus (VLB)
  - the first local bus to gain popularity
v) Peripheral Component Interconnect (PCI) Local Bus
  - most popular local I/O bus
vi) Accelerated Graphics Port (AGP)
  - AGP was develop in response to the trend towards greater and greater performance requirements for video.

·         PCI bus performance – PCI is the highest performance general I/O bus currently used on PCs
i) Burst mode
  - The PCI bus can transfer information in a burst mode where after an initial address is provided multiple sets of data can be transmitted in a row.
ii) Bus mastering
  - PCI supports full bus mastering, which leads to improver performance.
iii) High Bandwidth Options
  - the PCI bus specification version 2.1 calls for expandability to 64 bits and 66 MHz speed.

By Tang Ting Hang

Chapter 4: Memory System Architecture

1.) 8 Characteristic of Computer Memory Systems

2.) Memory Hierarchy

3.) Semiconductor Memory Types

a.) Read/ Write memory

        i.) DRAM (Dynamic Random Access Memory)

            - bits stored as charge in capacitors.

            - charges leak.

            - need refreshing even when powered.

       ii.) SRAM (Static Random Access Memory)

             - bit stored as on/off switches.

             - no charges to leak.

             - no refreshing needed when powered.

b.) Read Only memory (ROM)

        i.) PROM (Programmable Read-Only Memory)

           - can be programmed only ONCE.

           - nonvolatile, writing process performed electrically at a time
             later.

        ii.) EPROM (Erasable Programmable Read-Only Memory)

            - erased by UV and can be altered many times.

            - before write, all must be erased.

        iii.) EEROM (Electrically Erasable Read-Only Memory)

           - write at anytime without erasing prior contents electrically.

           -  location can be selectively erased and programmed.

        iv.) Flash Memory

            - a special type of EEPROM.

            - erase whole memory electrically, per block or per chip erasable.

4.) Cache

   - small amount of fast memory.

   - Immediate buffer between normal main memory and CPU.

   - may be located on CPU chip or module

 

 Cache operation

a.) CPU requests contents of memory location.

b.) check cache for this data.

c.) if present, get from cache (fast) = Cache Hit.

d.) if not present, read required block from main memory to cache = Cache Miss.

e.) then deliver from a cache to CPU.

f.) cache include tags to identify which block of main memory is in each cache slot. 

  Direct, Associative and Set Associative Mapping

 Cache Replacement

 - When the address accessed by CPU is not in cache, access has to be made to main memory.

 - Along with the required word, the entire block is transferred to cache.

 - But if cache is full, some existing cache memory is deleted to create space for the new entry.

 - So some replacement algorithm is needed.

5.) Cache Write Policy

= must not overwrite a cache block unless main memory is up to date.

 Two cases to consider when block that is in cache needs to be updated:

      a.) Write through
            = write the result in both the main memory and cache.
 

      b.) Write back
            = write in cache memory only to minimize memory writes.

6.) Complementary Metal Oxide Semiconductor (CMOS)

  - CMOS memory requires very little power to retain its contents. Usually powered by a battery.

  - CMOS stores vital data about the configuration of the computer system, even when the computer is turned off.

7.)Types of External Memory

      a.) Magnetic Disk
           - RAID
           - Removable (floppy)

      b.) Optical
           - CD-ROM
           - CD-Recordable (CD-R)
           - CD-R/W
           - DVD

     c.) Magnetic Tape
           - Casette

Calculation part ( Direct, Associative, and Set Associative)

 

        

 

                                                                                                                        
                                                                                                 By  Teoh Soon Gi